Dr. Ted Sun is a core faculty member at ITU. He previously served as an engineer at Integrated Device Technology, and Cadence where he developed design flows on both frontend and backend systems with a focus on design optimization, chip reliability, noise analysis, yield-awareness routing. He is also well experienced on EDA tools and system administration. His research has been featured in statistical electro-migration analysis on chip reliability and failure prediction.
Dr. Sun received his PhD in electrical engineering from Santa Clara University, Bachelor’s degree in Atmospheric Physics from the National Central University, Master’s in Management Science from University of Dayton.